Analysis and Design of an Area-Efficient Fastest Carry Look Ahead Adder with Enhanced Multiple Output Transmission Gate Logic

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Research areas:
Year:
2014
Type of Publication:
Article
Keywords:
Ripple Carry Adder, CLA, TG, Carry Generator, Carry Propagator, FA
Authors:
Prerana Shrivastava
Journal:
IJAIM
Volume:
3
Number:
1
Pages:
25-27
Month:
July
Abstract:
Adders are very important component of arithmetic and logical unit use in processors and digital computer systems. They are extensively use in basic digital operations such as subtraction, multiplication and division. The performance of adder operation is analyze by its power dissipation, layout area and its operating speed. The major drawback of the parallel adder is its slow speed due to the time it takes to propagate the carry. To overcome this limitation we propose the carry look ahead adder (CLA) design by using transmission gates which solves this problem by calculating the carry signals in advance, based on the input signals. The conventional CLA requires larger gate count as compare to the parallel adder, but it is a common philosophy that area can be traded off in order to achieve higher speed. In our work the use of transmission gate reduces the number of transistors which overcomes the area trade offs.
Full text: IJAIM_313_Final.pdf

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