Dynamic CMOS Based Digital Logic Circuits Evaluation Resurgence onto Performance Parameters

Research areas:

• Volume 2,Issue 5, March 2014

Year:

2014

Type of Publication:

Article

Keywords:

Dynamic CMOS, Precharge, Current Mirror, Pseudo NMOS, Current Mirror Keeper, PDN

Authors:

Seema Tiwari; Tarun Metta; Sandip Nemade

Journal:

IJAIM

Volume:

2

Number:

5

Pages:

132-136

Month:

March

Abstract:

The high performance digital circuits are designed with the dynamic CMOS circuits. There is different CMOS based digital circuits accepted time by time for improving the driven parameters to get better response. The static CMOS and dynamic CMOS based digital circuits are two common and important technics which employed for designing complex digital circuits. The static CMOS logic based digital circuit gives better noise immunity but slower in response as compare to dynamic CMOS based circuit. In high speed electronics clocked logic methodology plays important role, the clock signal is used to synchronise transistor in sequential logic circuits. Now a day’s dynamic CMOS logic circuits are used to get fast response up to acceptable noise level. In this paper a comparative evaluation is done for different accepted logic circuits based on dynamic CMOS technique. These techniques are Domino Technique, Mendoza Technique, Noise Tolerant Dynamic logic, Feed through logic, Conditional Clocking and Delayed Clocking based on principles such as Using keeper, Pre-charging internal nodes, Raising source voltage, Constructing complementary p-network, and Transparency Window Technique. Circuits designed using dynamic logic styles can be considerably faster and more compact than their static CMOS counterparts. This is especially the case with wide fan-in dynamic logic gates where a single gate can realize the logic function that otherwise would require multiple levels of static CMOS logic gates.

Full text: IJAIM_229_Final.pdf