Adiabatic Energy Recovery Circuit in Deep Sub Micron Technology

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Year:
2016
Type of Publication:
Article
Keywords:
CMOS, Adiabatic Technique, ECRL, PFAL, CAL, NMOS, PMOS
Authors:
Riju Nema; Ruby Tiwari
Journal:
IJAIM
Volume:
4
Number:
5
Pages:
173-176
Month:
March
ISSN:
2320-5121
Abstract:
Adiabatic switching method is use to suppress the dynamic power dissipation in CMOS circuits. This power dissipation is mainly cause during the time of output capacitive load charging and discharging time i.e. during the rise and fall time. The adiabatic technique is base and charge recovery concept. The current flow from supply voltage either Vdd or ground to output load capacitor is controlled in a way that the energy dissipation during the rise time or fall time and output load capacitor dissipation is reduced. This paper is base on adiabatic power dissipation technique for dynamic power dissipation reduction using deep submicron i.e. 50nm CMOS technology. The timing simulation and power dissipation analysis is done on MICROWIND layout simulator tool.
Full text: IJAIM_536Final.pdf

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