Synchronization Failure and Trade-offs for Sequential Circuits in 50 nm CMOS Technology

Research areas:

• Volume 4,Issue 4, Jan. 2016

Year:

2016

Type of Publication:

Article

Keywords:

Synchronization, Propagation delay, Setup Time, Hold Time, FSM, FIFO

Authors:

Sandeep Kumar Tiwari; Prof. Vinod Pathak

Journal:

IJAIM

Volume:

4

Number:

1

Pages:

149-152

Month:

January

ISSN:

2320-5121

Abstract:

In synchronization failure, metastability is one of the example. The syncronization failure creates a state where the bi stable device such as flip flop goes in to a unwanted state of output in in a level between logic high and logic low. After some time it may resolve this state to any stable logic level and retain the system performance. Microwind layout simulator is use to design the CMOS layout of latches and flipflops. The timing simulation along with parametrc analysis such as power , switching delays, number of transistors, data and clock frequencies etc is done on microwind simulator. For simulation a different frquency signals are applied on synchronous circuit, during every clock edge the relative time of the two signals changes a bit leading to synchronization failure.

Full text: ijaim-521-final.pdf