Computational Time, Latency, Throughput Improvement of Digit-Serial/Parallel Finite Field Multiplier

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Research areas:
Year:
2015
Type of Publication:
Article
Keywords:
Computational Time, Latency, Throughput Improvement, Digit-Serial or Parallel, Redundant Basis, Finite Field Multiplier
Authors:
Vinay Patel; Vinod Pathak
Journal:
IJAIM
Volume:
4
Number:
3
Pages:
114-116
Month:
November
Abstract:
In this work a novel recursive decomposition algorithm for Redundant Basis (RB) multiplication is use to obtain high-throughput digit-serial implementation. A parallel architecture using Manchester carry chain adder is design for this purpose. Since it gives faster addition in multiplication process with less number of transistors. The carries of this adder are computed in parallel by two independent 4-bit carry chains which reduce the carry chain length. The circuit is propose for 8-bit adder module with significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module. In this work the length of input sequence for multiplication is from two to eight.
Full text: IJAIM_505_Final.pdf

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