CMOS Synthesis of Multivalue Logic Base Quaternary 16X1 Multiplexer

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Year:
2015
Type of Publication:
Article
Keywords:
MVL, Ternary Logic, Quaternary Logic
Authors:
Md Irshad Alam; Jeewan Kumar; Dr. Rita Jain
Journal:
IJAIM
Volume:
4
Number:
3
Pages:
92-94
Month:
November
Abstract:
In CMOS transistor base binary digital circuits interconnection of metals consume large area with delay and power consumption penalty. Multivalue logic requires less interconnection, and carry more information on a single line. In this paper the multivalue multiplexing and decoding logic on 50nm technology is propose. For the design of 16X1 MVL multiplexer circuit transmission gate is use. The charging time of TG is proportional to its time constant RC, thus to increase the speed of circuit the switching resistance is reduce. The circuit is compatible with standard CMOS base circuits.
Full text: IJAIM_486_Final.pdf

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