Enhancement of Noise Tolerance in Dynamic CMOS Circuit with Keeper Transistor

Hits: 1596
Research areas:
Year:
2015
Type of Publication:
Article
Keywords:
Dynamic CMOS, MTCMOS, Static CMOS, Keeper Transistor, Single or Tripple Phase Sleep Signal
Authors:
Rupa Behre; Rahul Mishra
Journal:
IJAIM
Volume:
4
Number:
3
Pages:
86-88
Month:
November
Abstract:
Dynamic CMOS logic required less number of transistor for static CMOS design but they are inherently susceptible to noise. In dynamic CMOS logic the switching threshold voltage is equivalent to the switching threshold voltage of pull down NMOS transistor network. Whereas the switching threshold voltage of static CMOS circuit is nearly half to the supply voltage. Thus though Dynamic CMOS logic required less number of transistor for design of digital circuits but they are inherently susceptible to noise. Here the noise-tolerant dynamic CMOS circuit with good noise immunity, energy efficiency, speeds, and area, as compared to the existing techniques is discuss. For leakage power reduction in metal oxide semiconductor field effect transistor multithreshold CMOS (MTCMOS: (Multiple Threshold Complementry Metal Oxide Semiconductor)) technique is use.
Full text: IJAIM_484_Final.pdf

Indexed By