Low-Power Clocked Redundant Flip-Flop using Transmission Gate

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Research areas:
Year:
2015
Type of Publication:
Article
Keywords:
Transmission Gate TG, Master Slave FF MSFF, Master Slave Latch MSL, C2MOS Clock CMOS, Adaptive Couple AC, Short Channel Effects SCE, Flip flops
Authors:
Sapna Sadhwani; Dr. Rita Jain
Journal:
IJAIM
Volume:
4
Number:
2
Pages:
82-85
Month:
September
Abstract:
Flip-flop is the key block of sequential circuit which store binary bit. In this paper the flip-flops are designed with reduce number of transistor working on conditional precharge and the conditional capture technologies so as to reduce the redundant switching activities. It is designed by using transmission gate logic. Use of transmission gate not only reduces the number of transistors but also reduces the stray capacitances. Flip-flop power dissipation is almost equal to the transmission gate power dissipation.
Full text: IJAIM_483_Final.pdf

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