Time Efficient Implementations of Matrix Multiplication for Signal Processing

Research areas:

• Volume 4,Issue 2, Sept. 2015

Year:

2015

Type of Publication:

Article

Keywords:

VHDL VHSIC Hardware Description Language, PE Processing Element, FIFO First in First Out, RAM

Authors:

Rakhi Sharma; Soheb Munir

Journal:

IJAIM

Volume:

4

Number:

2

Pages:

74-76

Month:

September

Abstract:

The work in this paper is based on VHDL (Very High Speed Integrated Circuit Hardware Description Language) implementation of well-organized design of parallel matrix multiplication with reduce gate counts. The analysis of computational time will be done. The matrix multiplication operation use in many areas of scientific research like digital signal and image processing, microprocessor and microcontroller base design etc. The processing speed of this application is mainly affected due to data transfer latency between RAM memory. As the handshaking scheme requires the Block RAM accessing continuously until the comes out.. The individual processing elements blocks such as SRAM, multiplier, adders etc are designed and these modules are interconnected to form the main design by component instantiation in VHDL The results are simulated to demonstrate the accuracy and matrix size capacity of the architecture. The design is done on the basis of blocking and parallelization. Blocked matrix multiplication enables processing randomly large matrices using partial memory capability, and decrease the bandwidth requires across the device boundaries by recycle the existing elements. The propose algorithm verify low execution times while limiting the gate count.

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