Reducing the Chip Area and Power Dissipation of 4-Bit High-Speed Multioutput Carry Look-Ahead Adder using Transmission Gates in Domino CMOS Logic

Research areas:

• Volume 4,Issue 2, Sept. 2015

Year:

2015

Type of Publication:

Article

Keywords:

Carry Chains, Carry Look-Ahead CLA Adders, Manchester Carry Chain MCC, Multi Output Domino Logic, Transmission Gates

Authors:

Rajeshwari Gujamagadi; Yogesh Khandagre

Journal:

IJAIM

Volume:

4

Number:

2

Pages:

55-58

Month:

September

Abstract:

Adders are important parts of processor circuits. The demand for high performance processors is very high, so there is a need for improving the performance and functionality of adders. Carry look-ahead adder’s (CLA) principle and architecture remains dominant in the High-speed adder architectures, since the carry delay can be improved by calculating the carry in each stage in parallel. This is done by using the most common dynamic (domino) CLA adder, Manchester carry chain (MCC) block in multioutput domino CMOS logic. MCC is the most common architecture in VLSI. Implementation of wider adders based on the use MCC adder module improves the operating speed. But, consumes more chip area and power. It also is very large and complex in structure. To reduce the chip area we are proposing to use the Transmission Gates (TG) in Carry look-ahead adders, which occupy less space and have very less power dissipation. Design and simulation of the proposed technique have shown the reduction in chip area by 40-45%. The proposed technique reduces the power dissipation by 34%.

Full text: IJAIM_473_Final.pdf