CMOS Circuit Layout Design for Sub Threshold Leakage Power Optimization

Research areas:

• Volume 3,Issue 5, March 2015

Year:

2015

Type of Publication:

Article

Keywords:

CMOS, Circuit Layout, Threshold Leakage Power Optimization

Authors:

Sucheta Singh Muktawat

Journal:

IJAIM

Volume:

3

Number:

5

Pages:

263-266

Month:

March

ISSN:

2320-5121

Abstract:

The recent reduction in transistor size using scaling will cause sub threshold leakage currents to become an increasingly large component of total power dissipation. In this work a stack transistor technique using two series connected stack is use to design the digital circuit. The total leakage current is the function of inputs, thus we model the leakage current for each input states. The static and dynamic power of stack is considerably low. But it has a delay penalty and its area requirement is maximum compared with other processes. This can be overcome by using stack transistors of half size.

Full text: IJAIM-420_Final.pdf