CMOS Layout Design for Future High Performance Memories

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Year:
2012
Type of Publication:
Article
Keywords:
CMOS, High performance memory
Authors:
Deepak Sharma; Prof. Mukesh Tiwari; Prof. Jai Karan Singh
Journal:
IJAIM
Volume:
1
Number:
1
Pages:
63-66
Month:
December
ISSN:
2320-5121
Abstract:
Memories store ones and zeros. These ones and zeros are stored and either retrieved or manipulated. Most memories store data inputs to some location. Accessing one memory location among other memory locations is as simple as selecting a set of x-y coordinates. This paper focuses on circuit design techniques for high performance CMOS layout design of memories. In order to provide a framework for understanding the techniques and the issues behind them.
Full text: IJAIM-26 Final.pdf

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